Circuit and method for efficiently expanding compressed data stored in memory
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United States of America Patent
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Sep 29, 1998
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N/A
app pub date -
Jun 20, 1996
filing date -
Sep 30, 1994
priority date (Note) -
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Abstract
A variable bit-length code processing circuit includes first, second and third registers (12, 20, 22) each of which is of 1 word, and memory data is loaded to the first register (12), and a variable bit-length code is withdrawn from the third register (22). The second register (20) and third register (22) are coupled to a barrel shifter (16) which barrel-shifts data of 2 words according to a barrel shift amount which is applied by a subtracter (30) on the basis of the number of the valid bits and the number of the remaining bits.
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