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Abstract

A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained. The interface includes a selector circuit, such as a multiplexor or Q-switch, coupled to receive memory address signals and control signals from the graphics controller and the memory controller via a dedicated bus from each of these controllers. The selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller. The selector circuit is operable by a logic circuit, incorporated within the systems controller, which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row, or in the remaining DRAM rows.

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First Claim