Verification of accesses in a functional model of a speculative out-of-order computer system
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United States of America Patent
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Sep 29, 1998
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N/A
app pub date -
Oct 9, 1996
filing date -
Oct 9, 1996
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Abstract
A system and method for testing and verifying the correctness of cache accesses on a model or implementation of a processor that performs speculative and or out-of-order instruction execution. For each behavioral model of a processor under test in a simulation system, an architectural model is created that is fed the same instruction stream and system bus stimulus. The architectural model is capable of correctly and independently executing the instruction stream. The cache and TLB state of the architectural model are kept synchronous with those of the behavioral model under test. Cache synchronization is achieved by reporting, matching and verifying all speculative cache activity and all out-of-order cache accesses, move-ins and move-outs by the behavioral model as it occurs rather than in natural program order.
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