Processor array
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Sep 29, 1998
Grant Date -
N/A
app pub date -
Mar 1, 1996
filing date -
Mar 1, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A processor array 100 having an improved I/O pin utilization scheme. The inventive processor array 100 includes a first and a second set of processors 112 and 114 arranged within a chip boundary B1, with each of the processors 112 within the first set being positioned adjacent the chip boundary B1. The invention further includes an I/O arrangement for providing a plurality of electrical paths 136 across the chip boundary B1. A switch network is included for connecting each of the I/O paths 136 to a horizontal port 130 of an associated one of the processors 112 within the first set during a first clock cycle and for connecting each of the I/O paths 136 to a vertical communication port 132 of the associated processor during a second clock cycle.
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