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Abstract

A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same memory buffer. A display controller and a video MPEG engine contend for access to a DRAM memory buffer controller, and have their relative priorities set so that the video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when the display controller is reading from that same memory buffer, and to write to the memory buffer at a relatively fast speed during a time period when the display controller is not reading from the memory buffer. The relatively slow speed is preferably much slower than the reading speed of the display controller, while the relatively fast speed is preferably much faster than the display controller. The DRAM memory buffer controller has a limited memory transfer bandwidth; the display controller and the video MPEG engine are operated at speeds which completely occupy that bandwidth, with the display controller given higher priority. Thus, while the display controller is reading from the memory buffer, the video MPEG engine is constrained to operate at a relatively slow speed, and is unable to overtake the display controller, but while the display controller is not reading from the memory buffer (e.g., during a vertical retrace interval), the video MPEG engine is able to operate at a relatively high speed, and is able to write an entire frame to the memory buffer in a relatively short time.

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First Claim