Importance

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Abstract

Disclosed is a reusable hardware layout ('core') for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design. To implement the specified video core MPEG-2 functions, the video core employs, as architecturally distinct logic blocks, an inverse quantization unit, an inverse discrete cosine transform unit, a half pel compensation unit, a merge and store unit, and registers storing control information used by the other units.

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First Claim