Circuit technique for logic integrated DRAM with SIMD architecture and a method for controlling low-power, high-speed and highly reliable operation
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United States of America Patent
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Oct 6, 1998
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app pub date -
May 30, 1997
filing date -
May 30, 1997
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Abstract
In a logic integrated DRAM LSI with SIMD architecture, a intentional clock skew is introduced for both between DRAM blocks and between logic blocks due to reduce the magnitude of peak current, operation frequency and number of I/O are defined for both DRAM blocks (frequency f.sub.M, I/O number m) and logic blocks (frequency f.sub.N, I/O number n) to keep the relation of f.sub.M .times.m=f.sub.N .times.n, address out of order scheme is introduced to achieve a high-speed and low-power DRAM access.
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