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Abstract

A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus, over multiple time slices, the system can emulate many different types of memories.

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