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Abstract

The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars. The third embodiment uses two resist layers and a photo mask shifting (offset) technique to form small spaces between the electrodes. Lastly, a capacitor dielectric layer and a top electrode are formed over the bottom electrodes thereby completing the capacitor with a pillar structure.

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First Claim