Laterally situated stress/strain relieving lead for a semiconductor chip package
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United States of America Patent
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Oct 13, 1998
Grant Date -
N/A
app pub date -
Sep 6, 1996
filing date -
Sep 8, 1995
priority date (Note) -
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Abstract
A semiconductor chip package includes a substrate having a first surface and a second surface and a gap extending from the first surface to the second surface. The substrate defines a plane which is substantially parallel to the first and second surfaces. The substrate has conductive terminals accessible and the second surface and bond pads. Conductive leads extend across the gap whereby each lead electrically interconnects one of the conductive terminals and one of the bond pads. Each lead includes an expansion section within the gap which is laterally curved with respect to the plane. A semiconductor chip having a back surface and a face surface is assembled to the substrate. The face surface includes a plurality of contacts on the periphery of the face surface of the chip whereby the chip contracts are electrically connected to the bond pads on the substrate.
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