Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
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United States of America Patent
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Oct 13, 1998
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app pub date -
Oct 4, 1996
filing date -
May 26, 1995
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Abstract
An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.
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