CMOS high-speed differential to single-ended converter circuit
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United States of America Patent
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Oct 13, 1998
Grant Date -
N/A
app pub date -
May 23, 1996
filing date -
May 23, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.
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