Importance

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Abstract

An oscillator circuit having a flip chip metalization pattern and base substrate metalization pattern is defined such that a common-drain oscillator is configured with the common drain interposed between the source and gate terminals, providing an effective RF common reference with reduced parasitic inductance elements which otherwise degrade oscillator power and phase noise at high frequencies. Multiple sets of such patterns on the substrate and such three-terminal devices on the flip chip are arranged such that conductor patterns on the substrate connecting separately from the gates and the sources of the multiple devices to the common-drain reference are easily configured into separable tuning (or resonator) and feedback circuits. A common-drain oscillator having an interdigitated capacitor coplanar cavity resonator circuit as the gate input circuit having reduced distributed inductance is realized utilizing the interposed common-drain connections provided thereby. Having many small devices, such as FETs, coupled closely together (each having very low parasitic and therefore very high potential operating frequency), the signal power of each adds arithmetically but the noise power adds statistically thereby achieving lower phase noise relative to the combined oscillator signal power. Circuit structures utilizing this invention can provide very large oscillator arrays providing a reduction in phase noise relative to the oscillation signal without having the usual device size limitations.

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First Claim