Apparatus and method for minimizing DRAM recharge time
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United States of America Patent
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Oct 13, 1998
Issued Date -
N/A
app pub date -
Aug 7, 1997
filing date -
May 21, 1996
priority date (Note) -
Expired
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Abstract
A Dynamic random access memory has multiple registers dedicated to each column, and is controlled to refresh by reading multiple bit values from distinct capacitance storage cells consecutively, followed by consecutive refresh steps for the same capacitance storage cells equal in number to the number of consecutive read steps. As each bit value is read. it is stored in a distinct bit register reserved for that cell. The interleaved refresh provided minimizes DRAM access time, and provides a memory architecture wherein distinct, separate register arrays may be dedicated to and support distinctly different functions, such as servicing a CPU and a video system.
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