Importance

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Abstract

A clock synthesizer is disclosed that includes a phase-locked loop circuit having two modes of operation: a non-slewing mode of operation, and a frequency-slewing mode of operation. During the power-up of the system, the PLL is controlled to operate in the non-slewing mode of operation to effect rapid variations in the output frequency. A power-on reset circuit is disclosed which determines when the system is in the power-up interval, and generates a power-on-reset signal to so indicate. The PLL operates in a frequency-slewing mode after power-up to provide controlled transitions in the frequency of the output reference signal of the PLL. A phase-locked loop circuit having structure to implement both modes is provided, as well as an adjustable lock detector circuit. The output of the lock detector, a logical lock signal, is used to enable the frequency-slewing mode of the PLL circuit. During power-up, the power-on-reset signal is deasserted, and disables the lock detector from generating the frequency-slewing mode enable signal. The PLL thus operates in a non-slewing mode during power-up. After the power-on-reset signal has been asserted, the lock detector is permitted to generate the frequency-mode enable signal as soon as the PLL achieves phase lock. Once phase lock has been achieved, the enable signal from the lock detector places the PLL in a frequency-slewing mode. The phase-locked loop circuit includes structure that limits the rate of variation in the frequency of the output reference signal, as well as limits the UP, and DOWN signals, by way of a reference window signal mechanism, to ensure that the lock detector, after power-up, always detects lock to thereby generate the frequency-slewing mode enable signal.

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First Claim