Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
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United States of America Patent
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Oct 20, 1998
Issued Date -
N/A
app pub date -
Nov 1, 1996
filing date -
Oct 19, 1995
priority date (Note) -
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Abstract
A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
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