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Abstract

A non-volatile semiconductor storage apparatus which incorporates second bit lines connected to the sources of memory cell transistors arranged in a column direction, formed separately from the layer of first bit lines connected to the drains of the memory cell transistors arranged in a column direction. The apparatus is equipped with a system which can erase data byte by byte without enlarging the whole size irrespective of the provision of decoders in the first and second bit lines. A non-volatile semiconductor storage apparatus which erases data byte by byte by selecting a predetermined group of memory cell transistors by the source lines and the word lines connected to the diffusion area in the groups of memory cell transistors.

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First Claim