Importance

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Abstract

In a memory device, a write operation only to a desired memory location may be performed by recognizing an address transition and preventing a memory write to an undesired memory location in response thereto. The memory write to the undesired memory location may be prevented by blocking the memory write using an address transition detection (ATD) signal. This may include decoupling a bitline (e.g., using a passgate transistor) from a data signal in response to the ATD signal. Alternatively, the memory write may be prevented by pulsing an ATD signal to delay the memory write to the undesired memory location and then deasserting a data write signal to block the memory write. In one embodiment, a circuit which includes a memory cell and an isolation circuit coupled to the memory cell is provided. The isolation circuit may be configured to prevent a memory write to the memory cell in response to an ATD signal. By using the width of an ATD pulse to block the writing of an undesired memory location, the present invention provides improved address setup (t.sub.SA) and address hold (t.sub.HA) margins compared to solutions of the past. Preferably, the invention is implemented in a data write bus to bitline interface using passgate transistors to control access to a pair of bitlines by a data write bus. Alternatively, the invention may be implemented by combining an internal write signal with an ATD pulse in a data write bus driver within the memory device.

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First Claim