Method and apparatus for performance optimization in power-managed computer systems
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United States of America Patent
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Oct 20, 1998
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N/A
app pub date -
Sep 15, 1995
filing date -
Sep 15, 1995
priority date (Note) -
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Abstract
The performance of a computer system which use reduction of clock speed to conserve power is enhanced by dynamically adjusting the minimum number of clock cycles required for memory access ('wait states'). When the computer system decreases its clock speed, the minimum number of wait states is decreased to account for the longer cycle time. Likewise, when the computer system increases its clock speed, this invention determines whether any increase in the minimum number of wait states is required, and if so, implements such an increase.
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