Data processing device having split-mode DMA channel
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United States of America Patent
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Oct 20, 1998
Issued Date -
N/A
app pub date -
Aug 19, 1993
filing date -
Sep 28, 1990
priority date (Note) -
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Abstract
A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.
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