Mixed mode CMOS input buffer with bus hold
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United States of America Patent
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Oct 27, 1998
Grant Date -
N/A
app pub date -
Sep 12, 1996
filing date -
Sep 12, 1996
priority date (Note) -
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Abstract
A mixed-mode, overvoltage tolerant input buffer for interfacing to a tristate bus line is disclosed, the input buffer having a bus hold feature for maintaining the state of the input buffer output and bus line when the bus line enters into the tristate mode, the input buffer being capable of suppressing leakage currents from the bus input through the bus hold circuit to the input buffer power supply during overvoltage conditions. The bus hold circuit has a feedback inverter coupled between the output and the bus input for providing a stabilizing feedback signal to the bus input, the inverter being powered by a source voltage which is selectively coupled to the input buffer power supply, the source voltage being isolated from the input buffer power supply during overvoltage conditions.
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