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Abstract

An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock. Generally, the system can produce output clocks with 50% duty cycle and with rates greater than, equal to, or less than the external clock (EFI). Other optional operating modes generate 25% duty cycle waveforms at 1/2 the rate of EFI. A feedback signal is generated by comparing the phase of the generated on-chip clock with the phase of EFI which is used to adjust the overall delay of the generator in order to improve synchronism between EFI and the on-chip clock.

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