Importance

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Abstract

A graphics subsystem includes hardware for permitting tile texture data to be dynamically cached internally within the hardware. In addition, the system generates a SHIFT signal to permit automatic adjustment of tile texture parameters to facilitate retrieval of the cached texture maps. The system includes a 1 kbyte static random access memory internally disposed within a graphics processor to facilitate UV caching of the texture maps by the graphics processor. A cache controller also disposed within the graphics processor facilitates tile requests by other resources in the graphics subsystem to the internal static random access memory. The cache controller performs UV tile read hit comparisons and subsequent UV to linear address conversions to read texels from the internal static random access memory.

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First Claim