Compiling apparatus and method for promoting an optimization effect of a program
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United States of America Patent
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Oct 27, 1998
Grant Date -
N/A
app pub date -
Feb 23, 1995
filing date -
Feb 23, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A compiling apparatus and method in which instructions are scheduled for an efficient parallel process with a register allotting process and an instruction scheduling process performed independently of each other. An instruction scheduling unit collects information indicating the range of available registers, and renames registers by replacing the register numbers used by the instructions with other register numbers according to the collected register information and the analysis of definition/reference instruction dependency. The instructions are scheduled after the registers have been renamed.
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