System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
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United States of America Patent
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Oct 27, 1998
Issued Date -
N/A
app pub date -
Nov 19, 1996
filing date -
Sep 30, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention teaches a new system for transferring data between a network and hosts coupled to the network. The system uses an adapter, that is coupled between the host and the network, to allow segmenting and reassembling cells directly in the host memory. The present invention also teaches a pipelined DMA architecture to overcome the problem of the interruption of the DMA operation when switching from one virtual circuit to the next. This architecture depends on fast access to a local memory used for storing buffer descriptors for each virtual circuit. In this architecture, a two stage pipeline is used with the first stage performing the local memory access while the second stage performs the DMA transfers. When the pipeline is filled, both stages will operate in parallel yielding significant gain in performance due to continuous operation of the DMA.
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