Memory system with multiplexed input-output port and systems and methods using the same
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United States of America Patent
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Oct 27, 1998
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N/A
app pub date -
Apr 24, 1996
filing date -
Apr 24, 1996
priority date (Note) -
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Abstract
A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.
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