Multiprocessor system having a large number of processor system components connected to a plurality of serial high-speed-buses
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United States of America Patent
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Oct 27, 1998
Issued Date -
N/A
app pub date -
Nov 21, 1997
filing date -
Aug 19, 1992
priority date (Note) -
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Abstract
A multiprocessor system has a plurality of serial system buses arranged in parallel to which is connected a large number of system components (PSK1, PSK, SSK). The system components (PSK1, PSKm, SSK) are processor system components (PSK1, PSKm) having cache memories and memory system components. Every system component (PSK1, PSKm, SSK) is connected to every serial system bus. The processor system components (PSK1, PSKm) have the capability for maintaining the consistency of the contents of the cache memories for every serial high-speed bus (SB1, SBn-1, SBn).
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