Address strobe recognition in a memory device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 3, 1998
Issued Date -
N/A
app pub date -
Jul 9, 1997
filing date -
Nov 6, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully