Method for testing cache memory systems
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United States of America Patent
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Nov 3, 1998
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N/A
app pub date -
Jun 17, 1996
filing date -
Jun 17, 1996
priority date (Note) -
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Abstract
A method for testing cache memory components of a computer system. The method tests RAM by detecting whether external memory caching can be disabled via software, and if not, the RAM is tested in segments large enough to ensure overflow of the primary L1 and secondary L2 CPU cache memory. The size of the L1 and L2 cache memories are measured by timing memory access speeds in Kb/Sec of successively larger blocks of memory. Additionally, a method for testing a particular region of system memory is provided, even if the memory region is in use by the operating system, which is accomplished by creating an isolated environment that switches the operating system off and on for each pass of the memory test.
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