Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 3, 1998
Grant Date -
N/A
app pub date -
Jan 26, 1996
filing date -
Jan 26, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a parity bit for the two status bits. A programmable array logic control unit has a predictive generator logic unit to generate the proper 'status parity bit' for each set of status bits (V,R) without need for waiting to calculate the status parity bit from the existing values of the two status bits.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully