Realtime hardware scheduler utilizing processor message passing and queue management cells

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United States of America Patent

PATENT NO 5832262
SERIAL NO

08528267

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Abstract

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This invention discloses a hardware manager and scheduler device which can be implemented within a distributed operating system. The scheduler replaces software synchronization and interaction with two unit-level hardware units that facilitate task scheduling. These units utilize global machine memory to manage scheduling queues using a simple algorithm. The 'tasks' managed may be programs requiring execution by a processor, other shared system resources that must be cooperatively scheduled, or input/output queues through system peripheral connections. One unit manages tasks waiting to be executed while the other unit manages tasks which have been completed. Each unit reads and writes pointers to task control blocks stored in a shared memory into and from one or more circular memory queues stored separately in the shared memory. Each queue may correspond to a particular task priority and may be separately managed by the device of this invention.

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Patent Owner(s)

Patent OwnerAddress
LORAL FEDERAL SYSTEMS COMPANYFSC HQ/MS LEGAL DEPARTMENT 6600 ROCKLEDGE DRIVE BETHESDA MD 20817

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bezek, John D Owego, NY 7 296
Johnson, Christopher T Endicott, NY 3 65

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