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Abstract

A variable length decoder (VLD) for processing an input bit stream (e.g., MPEG video) which includes qualifying and non-qualifying types of variable length code words. The VLD includes an input circuit for receiving the input bit stream and providing a sequence of available input bits, a shifter circuit for providing a decoding window that includes one or more code words contained in the sequence of available input bits, a code word length decoding circuit for determining whether or not the decoding window contains a pair of qualifying code words, and for determining the combined length of the pair of qualifying code words and producing a combined length signal representative of the determined combined length, if the decoding window contains a pair of qualifying code words, and further, for determining the length of a leading code word contained in the decoding window and producing a leading word length signal representative of the determined length of the leading code word. The VLD also includes a computation loop circuit for generating a word pointer signal, in response to the combined length signal if it is determined that the decoding window contains a pair of qualifying code words, or otherwise, in response to the leading word length signal. The shifter circuit is responsive to the word pointer signal for shifting the decoding window across the sequence of available input bits. A related method is also disclosed.

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First Claim