Address space architecture for multiple bus computer systems
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United States of America Patent
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Nov 10, 1998
Issued Date -
N/A
app pub date -
Jun 24, 1996
filing date -
Jun 20, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.
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