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Abstract

A pipelined microprocessor containing a classifying circuit is provided. The classifying circuit allows an associated pipeline stage to implement a function requiring a larger number of cascaded logic levels than the clock cycle of the microprocessor will allow. The classifying circuit is especially useful with a pipeline stage which implements a 'fundamental limit' function (i.e. a function that does not naturally divide into component functions which could be implemented as separate pipeline stages). When an evaluation time larger than a clock cycle is required, the classifying circuit holds the associated pipeline register, thus allowing the circuit to continue uninterrupted with its evaluation. The time interval available for the fundamental limit stage is dynamically extended. Furthermore, in cycles where the fundamental limit function is not required to evaluate, the pipeline operates at a significantly higher clock rate.

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First Claim