Packed/add and packed subtract operations
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United States of America Patent
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Nov 10, 1998
Grant Date -
N/A
app pub date -
Mar 4, 1996
filing date -
Mar 4, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed length data elements. The data elements can be eight bits, sixteen bits or thirty-two bits in length. The circuit performs the operation on the first data element from the first packed data and the first data element from second packed data, producing a first result data element. The circuit performs this operation on the next data element from the first packed data and the next data element from the second packed data, producing a next result data element. This continues for all the data elements in the first and second packed data. The result data elements constitute a result packed data that is stored in the destination register.
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