Special test modes for a page buffer shared resource in a memory device
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United States of America Patent
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Nov 10, 1998
Issued Date -
N/A
app pub date -
Sep 25, 1996
filing date -
Jun 30, 1993
priority date (Note) -
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Abstract
A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
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