Memory system with write buffer, prefetch and internal caches
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United States of America Patent
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Nov 10, 1998
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N/A
app pub date -
Aug 6, 1990
filing date -
Aug 6, 1990
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Abstract
A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.
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