Importance

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Abstract

A programmable logic array integrated circuit has a plurality of regions of programmable logic. Each region includes a plurality of logic modules, each of which is programmable to perform any of several logic functions on input signals applied to the module. Each module also includes a register for selectively registering a signal produced in or applied to the logic module. Signals for controlling the register and possibly other functions of the module are selected on a region-wide basis to reduce the amount of architecture control memory that each region must have. Each register may be operated as either a flip-flop or a flow-through latch. The modules may be interconnected in a carry chain. The main output of a first module in such a chain may be fed back to the carry in input of that module to avoid having to use another module to generate a carry in signal for the first module in the chain.

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First Claim