Alignment of parity bits to eliminate errors in switching from an active to a standby processing circuit
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United States of America Patent
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Nov 17, 1998
Grant Date -
N/A
app pub date -
Apr 28, 1995
filing date -
Apr 28, 1995
priority date (Note) -
Expired
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Abstract
Glitchless switching between active and standby telecommunication apparatus having hierarchical nested parity bits is provided. A higher order parity bit is calculated based on defined data as well as a lower order parity bit. A method is provided for aligning each parity bit generated by a standby processor with a corresponding parity bit independently generated by an active processor. This alignment is accomplished prior to output frames of data being supplied by the standby processor in order to provide glitchless switching such that the first frame of data supplied by the standby processor contains parity bits which are in agreement with the corresponding data in the frame.
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