Logical, fail-functional, dual central processor units formed from three processor units
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 17, 1998
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Dec 17, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computing system includes a pair of central processor units structured to operate in substantial synchronism to each execute the same instruction at substantially the same moment in time of identical instruction streams to achieve a logical central processor unit with fail-functional operation. One of the central processor units includes a pair of processors that execute, instruction by instruction, the instruction stream with checking for fail-fast operation. The other central processor unit includes only a single processor element. The system achieves a low cost fail-functional architecture.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully