Computer product for precise architectural update in an out-of-order processor
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United States of America Patent
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Nov 17, 1998
Grant Date -
N/A
app pub date -
Jun 25, 1997
filing date -
Jun 25, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
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