System for DMA controller sharing control signals in conventional mode and having separate control signals for each number of channels in distributed mode
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United States of America Patent
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Nov 17, 1998
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N/A
app pub date -
Apr 26, 1996
filing date -
Dec 11, 1995
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Abstract
A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.
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