Process for making a semiconductor MOS transistor
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United States of America Patent
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Nov 24, 1998
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N/A
app pub date -
Jul 23, 1997
filing date -
Dec 16, 1993
priority date (Note) -
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Abstract
The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.
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