Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP
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United States of America Patent
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Nov 24, 1998
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app pub date -
Oct 4, 1995
filing date -
Oct 4, 1995
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Abstract
A method for increasing the oxide removal rate of oxide chemical-mechanical polishing is provided for planarizing dielectric layers. The method of the invention is employed in the process for forming multilayer interconnects. The process employs doped oxide deposition and polish processing instead of undoped oxide deposition and polish. Doped oxides such as BPTEOS (boron phosphorous tetra-ethyl orthosilicate), BSG (boron silane-based glass), PSG (phosphorous silane-based glass), and BPSG (boron phosphorous silane-based glass) can be used. The polish rate of doped oxide film is 2 to 3 times the polish rate of undoped oxide film. By forming the planarized dielectric layers from doped oxide films, the throughput of the CMP process step is increased thus reducing the cost of manufacturing.
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