Importance

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Abstract

A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

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First Claim