US Patent No: 5,845,098
Number of patents in Portfolio can not be more than 2000
Address lines load reduction
Stats
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Dec 1, 1998
Issued date -
Jun 24, 1996
filing date -
08/669,680
serial no -
In Force
status
Importance
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Abstract
Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,359,717 Microprocessor arranged to access a non-multiplexed interface or a multiplexed peripheral interface | 28 | 1993 | |
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| 5,638,520 Method and apparatus for distributing bus loading in a data processing system | 7 | 1995 | |
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| 5,148,539 Address bus control apparatus | 19 | 1991 | |
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| 4,286,321 Common bus communication system in which the width of the address field is greater than the number of lines on the bus | 75 | 1979 | |
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| 5,473,575 Integrated circuit I/O using a high performance bus interface | 110 | 1992 | |
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| 5,235,684 System bus having multiplexed command/ID and data | 22 | 1988 | |
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| 4,374,410 Data processing system | 21 | 1979 | |