Address lines load reduction

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United States of America Patent

PATENT NO 5845098
SERIAL NO

08669680

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

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Patent Owner(s)

  • FREESCALE SEMICONDUCTOR, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baron, Natan Oranit, IL 10 85
Galanti, David Natania, IL 5 45
Kloker, Kevin Palatine, IL 1 0
Zmora, Eitan Jerusalem, IL 9 52

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