Importance

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Abstract

A semiconductor memory device such as a DRAM has an internal oscillator to provide a periodic clock signal. During a read operation, output data is generated synchronized to the internal clock signal, and an external control signal is provided also synchronized to the internal clock signal. A requesting device utilizes the external control signal for fetching data from the memory device at high speed with improved setup and hold time. The control signal output is active only during a read operation, thereby reducing power consumption. Additionally, a common line is used for receiving address, instructions, and data. This drastically reduces the number of pins for interfacing to a memory device.

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First Claim