Optimized routing scheme for an integrated circuit/printed circuit board
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United States of America Patent
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Dec 8, 1998
Grant Date -
N/A
app pub date -
Jun 20, 1997
filing date -
Jun 20, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board. As a result, the number of via plugs required for routing the first supply voltage through the printed circuit board is reduced, thereby increasing the layout area available for routing conductive traces in other layers of the printed circuit board.
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