Full subtracter
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United States of America Patent
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-
Dec 8, 1998
Grant Date -
N/A
app pub date -
Aug 22, 1996
filing date -
Aug 24, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An improved full subtracter is disclosed which receives a minuend signal A having a weight of +1, a subtrahend signal B having a weight of -1 and a borrow input signal Xi having a weight of -1 and provides a difference output: signal D having a weight of +1 and a borrow output signal Xo having a weight of -2. The full subtracter is composed of CMOS transistors such that both the signal D delay time and the signal Xo delay time are decreased by reducing the number of logic gate stages.
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